Time

Event

2:30 pm - 3:00 pm

Registration

3:00 pm - 3:05 pm

Welcome and NASCUG Business

Jack Donovan, ESLX Inc.

3:05 pm - 3.15 pm

SystemC IEEE Standardization  

Victor Berman, Cadence Design Systems, Inc.

Introduction to the SystemC TLM Standard & Path to IEEE Standardization

Stuart Swan, Cadence Design Systems, Inc.

3:35 pm - 3:55 pm

Transaction Level Modeling and Verification in SystemC

Adam Rose, Mentor Graphics, UK

3:55 pm - 4:15 pm

Towards A Heterogeneous Simulation Kernel for System Level Models in SystemC

Hiren Patel, Sandeep Shukla, Virginia Tech.

4:15pm - 4:35 pm

Modeling Dynamic Reconfiguration of FPGAs with SystemC 2.1

Adam Donlin, Xilinx.

4:35 pm - 4:55 pm

Platform Aware Algorithm Design Framework

Kota Bhaskar, Element CXI

4:55 pm - 5:15 pm

Modeling Software Interrupts using SystemC

David Black, ESLX Inc

5:15 pm - 5:20 pm

Wrap Up and Door Prize Give Away

5:20 pm - 6:00 pm

SystemC Networking and Beverages