18th NASCUG Meeting

6 June 2012

1:30 - 2:00 Pm Registration
2:00 - 2:10 Pm Welcome, Agenda & Introduction
David Black, NASCUG Program Committee
2:10 - 2:20 Pm SystemC Update from Accellera Systems Initiative
Mike Meredith, Accellera Systems Initiative
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2:20 - 2:40 PM Keynote: A Sneak Preview of the Upcoming SystemC AMS 2.0 Standard
Martin Barnasconi, SystemC AMS Working Group Chair
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2:40 - 3:00 PM A Comparison of TLM Modeling Styles' Performance and Accuracy
Bill Bunton, LSI, USA
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3:00 - 3:20 PM An Open-Source, Standards-Based Library for Achieving Interoperability Between TLM Models in SystemC and SystemVerilog
Adam Erickson, Mentor Graphics Corporation, USA
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3:20 - 3:40 PM Modeling of Automotive Wheel-speed Sensor ICs in SystemC
Friedrich Rasbornig, Infineon, Austria
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3:40 - 4:25 PM Poster Session / Social & Break
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SOC Virtual Prototyping: An Approach towards fast System-On-Chip Solution

Mamta Chalana, STMicroelectronics, Bangalore
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4:25 - 4:45 PM Beyond TLM 2.0: New Virtual Platform Standards Proposals from ST and Cadence
Stuart Swan, Cadence Design Systems, USA
Jerome Cornet, STMicroelectronics, USA
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4:45 - 5:05 PM Hybrid Simulation of Digital and Analog Models: A Study Towards Understanding Various Analog Modeling Methods
Tor Jeremiassen, Texas Instruments, USA
Abhilash Nair, Texas Instruments, India
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5:05 - 5:25 PM Using Formalized Programming Sequences for Higher Quality Virtual Prototypes
Jack Donovan, Duolog Technologies Ltd., Ireland
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5:25 - 5:45 PM Bridging the Gap: Consistent SystemC Code Generation for Multi-Abstraction-Level State Charts
Rainer Findenig, Upper Austrian University of Applied Sciences, Austria
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5:45 - 6:00 PM Closing Remarks & Awards, Poster Session Continued

 

 

Abstracts

A Sneak Preview of the Upcoming SystemC AMS 2.0 Standard

In 2010, the SystemC AMS 1.0 standard was released. It was first language targeting abstract mixed-signal modeling for system-level design and verification. The AMS extensions provided a uniform SystemC-based modeling style that can be combined easily with digitally-oriented ESL design methods such as TLM-2.0 to enable virtual prototyping of AMS systems. The AMS 1.0 standard introduces new execution semantics and language constructs for efficient simulation of discrete- and continuous-time modeling approaches. Complementary to these capabilities, the upcoming AMS 2.0 standard features extensions to these semantics to better model dynamic and reactive mixed-signal behavior at high levels of abstraction. This keynote will give a sneak preview on the innovations that are part of this upcoming AMS 2.0 standard, including the rationale behind the introduced technologies and a perspective on industrial mixed-signal applications.

 

A Comparison of TLM Modeling Styles' Performance and Accuracy

SystemC Transaction-Level Models (TLM) are now used in many stages of the SoC design cycle. Common TLM usages include architecture models for performance analysis, virtual prototypes for software development, and high-accuracy models for SoC performance validation. Common terminology for TLM modeling styles includes loosely timed (LT), approximately timed (AT), clock count accurate (CCA), and cycle accurate (CA). Though not clearly defined, each of these modeling styles implies a tradeoff between accuracy and simulation speed. To compare the performance and accuracy of modeling styles, an existing (CCA) model of the Axxia 3448 memory subsystem was simplified and used as a modeling style test bed. New AT and LT models of the simplified memory subsystem were created matching the functionality of the original model. Traffic generators were used to compare the performance and accuracy of the three modeling styles.

 

An Open-Source, Standards-Based Library for Achieving Interoperability Between TLM Models in SystemC and SystemVerilog

The IEEE-1666 2011 SystemC standard defines Transaction-Level Modeling (TLM 2.0) interfaces and semantics for conveying transaction objects between models. An approximate definition of TLM2 was defined in the Accellera Universal Verification Methodology (UVM) standard, a base class library and methodology for constructing reusable verification environments with IEEE-1800 2009 SystemVerilog. This presentation describes and shows examples of using UVM Connect (UVMC), a free, open-source library that enables interoperability between TLM models in both SystemC and SystemVerilog. UVMC also provides a command API for controlling UVM runtime simulation from SystemC. Unlike prior work, UVMC is fully based on standard technologies, is portable across multiple vendors' simulators, and imposes few restrictions on established modeling practices in either language. New use models that leverage the strengths of both languages are now possible, e.g., using SystemC components as reference models in a UVM testbench and verifying SystemC components using constrained random stimulus from SystemVerilog.

 

Modeling of Automotive Wheel Speed Sensor ICs in SystemC

Sense & Control, a department of Infineon Technologies Austria has been using SystemC models for mechanical, thermic and electrical investigations regarding the behavior of sensor IC for several years. With these models it is possible to review the sensor performance in a dedicated application environment. To reduce the risk of misinterpretation of the customer specification, our SystemC models are embedded in Matlab/Simulink testbenches (black-box approach) and provided to customers for pre-silicon verification. These SystemC models are used for VHDL cosimulation of an internal verification before tapeout of a new sensor product is done. This approach results in a shorter development phase and avoids expensive and time consuming redesigns. Currently Infineon is investigating additional tools to convert synthesizeable VHDL blocks directly to a SystemC model for internal and customer evaluations. In this presentation, a SystemC model of a wheel speed sensor IC (for ABS applications) will be described.

 

Beyond TLM 2.0: New Virtual Platform Standards Proposals from ST and Cadence

This talk will present several new TLM standards proposals that have been jointly developed by ST and Cadence and that are complementary to the existing SystemC TLM 2.0 standard. These proposals were developed based on extensive industrial virtual platform modeling experience over many years at ST and Cadence. Together with TLM 2.0 these new proposals enable interoperable Virtual Platform IP models to be developed, distributed, and integrated. We will discuss the motivation for each proposal as well as the technical approach that was selected. These proposals are available now to anyone in open source form under an Apache 2.0 license and will be submitted to Accellera for standardization.

 

Hybrid Simulation of Digital and Analog Models: A Study Towards Understanding Various Analog Modeling Methods

Currently, there is wide acceptance of modeling digital systems in SystemC. More and more, designers are moving away from Verilog and VHDL and performing more modeling using SystemC due to SystemC's strong behavioral modeling capabilities and faster simulation speeds. There is still a large void in the adoption of SystemC for analog simulation, primarily due to less awareness and various challenges of analog modeling using SystemC AMS. This paper describes a three-phase study of analog and digital co- simulation and provides pros and cons of different modeling methods.

 

Using Formalized Programming Sequences for Higher Quality Virtual Prototypes

Virtual prototypes have become an enabling methodology to allow software to be developed within market time constraints despite increasingly complex SoCs and Systems. The reliance on this methodology makes it imperative that the virtual prototype be a high-quality, accurate model to not impair efficient software development. This presentation will describe a methodology where a common suite of formal programming sequences and constraints can be used across the hardware, virtual prototype, and software domains to ensure high quality and consistency throughout. These formal programming sequences describe the complete hardware and software interface of the IP blocks including how to use the IP block in addition to the usual set of register descriptions. Detailed examples will be presented that show how these formal programming sequences are used to create common test cases that are applicable to TLM unit test, virtual prototype testing, RTL unit testing, and RTL SoC verification.

 

Bridging the Gap: Consistent SystemC Code Generation for Multi-Abstraction-Level State Charts

We present a UML- and SystemC-based methodology for single‐source hardware modeling on different abstraction levels, from untimed to cycle‐callable. Our approach uses an extension to UML State Charts that allows specifying all desired abstraction levels of a model in a single source and incorporates a generator that can automatically select a given abstraction level and transform the model into SystemC code that can readily be incorporated into existing virtual prototype platforms. Our approach aims to be easy to learn and apply by reusing well‐known industry standards. The behavior specification is based on UML State Charts and the interface specification uses a metamodel that can import existing formats such as IP‐XACT. The single‐source modeling provides several benefits over traditional top‐down modeling approaches, both during development and debugging. We successfully employed cycle‐callable models based on our approach in an RF transceiver virtual prototype and are currently piloting event‐driven models.

 

Poster Session

The poster session provides in-depth details of the user's presentation at the meeting. It includes an explanation of the context and motivation of the contribution, details of the innovation and explanation of results. Supporting charts, graphs and tables are presented and discussion and user interaction is encouraged.

 

 

Thanks to our sponsors

ARM Cadence CircuitSutra
Mentor Graphics Synopsys Forte Design Systems

 

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