ARMs IP at the PV level and SystemC TLM 2.0
Nizar Romdham, ARM, UK

Programmers' View (PV) implementations of ARM IP are configured and deployed by using ARM's RealView System Generator tool to produce self-contained simulations or incomplete platforms with dangling SystemC TLM 2.0 interfaces. ARM terms these simulations "Virtual Targets" with software development envisaged as the main use case.

TLM was chosen as an interface mechanism because of its status as a de facto standard. Because of TLM’s protocol agnosticism, ARM defines an additional layer on top of it, AMBA-PV, which defines a standard for how AMBA 3 AXI (AXI) transactions are propagated across a PV interface and provides containers for the AXI sideband signals (defining cacheable, bufferable, secure, locked and exclusive memory regions).

AMBA-PV is factored into two layers, a transport layer which is closely bound to the TLM transport layer and a user layer which is closer in semantics to the AXI protocol itself. Adding TLM interfaces to an ARM PV sub-system is performed within System Generator GUIs. Protocol converters from the System Generator internal bus, PVBus, to and from AMBA-PV are provided as well as a mechanism for defining externally visible master and slave signal and transaction ports. Protocol conversions from PVBus to non AMBA protocols are supported within the tool. Three distinct scheduling mechanisms are present in a hybrid System Generator, SystemC platform. The ARM and SystemC sub-systems contain local schedulers that are slaved to a master scheduler. The API to the master scheduler offers controls for the clock rates of both sub-systems and allows an arbitrary synchronization granularity to be set. An additional API on the ARM sub-system is published that allows access to system parameterization, for example, memory size.