An Approach to Reusing Architectural Models
Abhilash Nair, Texas Instruments (India) Pvt. Ltd, India

SystemC has emerged as the most popular language for simulation by IP architects and designers to do early architectural exploration. ESL tools used for Co-design and System Simulation have adopted this as an IP description and integration language. It provides syntax which mirrors hardware description languages (HDL). This gives great flexibility to easily capture both the functional and timing detail of an IP at micro architectural level.

Though the development of the architectural model starts from higher abstraction, it is enhanced with more micro architectural details such as modeling detailed pipeline stages, intermediate buffers, timing delays etc. In due course, such a model gets transformed to a very low abstraction level which very closely matches the design RTL. These models are very accurate, but they run at very slow speed (often less than 10 Kilo Cycles per second (KCPS)). This performance is largely sufficient for architectural exploration and design verification.

However, these models are practically not usable in simulation platforms for application software development, debugging and optimization, where the simulation has to run at thousands of kilocycles to millions of cycles per second. This is very critical and has a direct impact on the software development time.

This paper tries to address the above issue by defining some guidelines to improve the performance of an architecture evaluation model to meet the performance needs for application development.

Some of the methods used to improve performance include:

• Remove all SC_THREADS and replace with SC_METHODS
• Remove all SystemC data types in critical path and replace with C++ standard data types
• Remove clock sensitized process with event sensitized process

This paper also presents a case study of the above approach on a Memory Subsystem which consists of multiple cache modules and internal memories. The case study explains a step by step approach used to improve the performance of the model, and the resulting speed-up.