6th NASCUG Meeting

Time	Event
8:30 - 9:00 am	Registration/Continental Breakfast
9:00 - 9:05 am	Welcome & Agenda Jack Donovan, ESLX, Inc
9:05 - 9:15 am	OSCI Update Pat Sheridan, Executive Director, OSCI
9:15 - 9:20 am	NASCUG History Jack Donovan, ESLX, Inc.
9:20 - 9:55 am	Using Programmer’s View Timing Annotation for the Creation of Reusable TLM Models Asheesh Khare, CoWare, Inc. Tim Kogel, CoWare, Inc.
9:55 – 10:15 am	Practical Co-simulation with Cycle-callable Models Herve Alexanian, Sonics, Inc.
10:15 –10:35 am	PowerSC: A SystemC Framework for Power Estimation Felipe Klein, Computer Systems Laboratory/UNICAMP Guido Araujo, Computer Systems Laboratory/UNICAMP Rodolfo Azevedo, Computer Systems Laboratory/UNICAMP
10:35-10:45 am	Break
10:45-11:20 am	SystemC Exports and Hierarchical Channels for Efficient Data Conversion and Loopback David C Black, ESLX, Inc. Rosa Carbonell Mann, ESLX, Inc.
11:20-11:40 am	Language Extensions to SystemC: Process Control Constructs Bishnupriya Bhattacharya, Cadence Design Systems, Inc. John Rose, Cadence Design Systems, Inc. Stuart Swan, Cadence Design Systems, Inc.
11:40-11:55 am	Lunch
11:55-12:50 pm	PANEL - SystemC: A User’s Perspective What’s Working and What Needs to be Improved Moderated by: Jack Donovan, ESLX Organized by: Steve Pollock, JEDA Technologies Panelists: Terry Doherty Principal Engineer, Emulex Bill Dittenhofer Development Engineer, Processor Design Lab, Hewlett-Packard Trevor Wieman Member Technical Staff, ESL Modeling & Development Intel Ultra Mobility Group Victor Leonov Distinguished Member of the Technical Staff, Motorola Tor Jeremiassen Member Group Technical Staff, Advanced Architecture and Chip Technology, Texas Instruments
12:50-1:00 pm	Door Prize and Wrap Up