5th NASCUG Meeting

Time	Event
1:30 - 2:00 pm	Registration
2:00 - 2:05 pm	Welcome
2:05 - 2:25	Patterns and Issues in SystemC Usage John Aynsley, Doulos
2:25 - 2:45	Effective Performance Analysis and Visualization of SystemC Models Adam Donlin, Xilinx Inc.
2:45 - 3:05	High-Speed Hardware/Software Co-Verification with CPU Model Generator from Software Code Dai Araki, InterDesign Technologies Inc.
3:05 - 3:25	Cycle Accurate Transaction Level Modeling Using the ARM RealView ESL APIs Nizar Romdhane, ARM Inc.
3:25 - 3:40	Break
3:40 - 4:00	Behavioral SystemC Implementation of an MP3 Decoder Portavales Goldstein, State University of Campinas - UNICAMP
4:00 - 4:55	PANEL: Exploring the "Futures" of SystemC Moderated by: Mark McDermott, Adjunct Professor, University of Texas; Vice President, Engineering, Coherent Logix, Inc. Built upon the cooperative effort of combined vendor technology and user experiences, the IEEE has approved the SystemC language as IEEE Std. 1666. Providing a core for virtually all modeling and verification for system-level design, IEEE 1666 provides the foundation for the next generation of technologies and tools developed around the standard. Help us explore what the future holds for this new standard! As we move to even larger systems, how far can the language go in solving even more complex design challenges? PANELISTS Functional Verification: Kota Bhaskar, ElementCXI Mixed Signal Modeling: Dr. Joanne DeGroat, Associate Professor, Ohio State University RTOS Modeling: David Black, CTO, ESLX, Inc; Member, OSCI Language Working Group System Level Design: Mark Burton, Founder, GreenSocs; Chairman, OCP-IP SLD Working Group
4:55 - 5:00	Prize Drawing
5:00 - 6:00	Beer and Wine Reception